(sigemb-info 616) CfP for Track D8 (Networks-on-Chip) at DATE 2012

[Hiroki Matsutani <matutani@xxxxxxxxxxxxxxxxx>]

SIGEMB-ML のみなさま、

慶應大学の松谷です。重複して受理された場合はご容赦ください。
DATE 2012 トラック D8（Networks-on-Chip）の CfP をご案内させていただき
ます。ご検討いただければ幸いです。どうぞよろしくお願いいたします。

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                      CALL FOR PAPERS DATE 2012

                  TRACK D: "Design Methods and Tools"
                     TOPIC D8: "Networks-on-Chip"

           DESIGN AUTOMATION AND TEST IN EUROPE CONFERENCE
                       ICC, DRESDEN, GERMANY
                        12TH-16TH MARCH 2012
http://www.date-conference.com
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DEADLINES
- Paper Submissions           September 11, 2011
- Special Session Proposals   September 11, 2011
- Tutorial Proposals          September 11, 2011
- Notification of Acceptance  November 14, 2011
- Camera-Ready Paper          December 12, 2011
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QUICK LINKS
- Conference http://www.date-conference.com
- Call for Papers http://www.date-conference.com/final-call-for-papers
- Author Instructions http://www.date-conference.com/authors-instructions_cfp
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The 15th DATE conference and exhibition is the main European event bringing
together designers and design automation users, researchers and vendors, as
well as specialists in the hardware and software design, test and
manufacturing of electronic circuits and systems.

The five-day event consists of a conference with plenary invited papers,
regular papers, panels, hot-topic sessions, tutorials and workshops, two
special focus days and a track for executives. The scientific conference is
complemented by a commercial exhibition. The organisation of user group
meetings, fringe meetings, a university booth, a PhD forum, vendor
presentations and social events offers a wide variety of extra opportunities
to meet and exchange information. Special space will also be allocated for
EU-funded projects to show their results.

You are invited to submit your research contributions to the Topic D8

                      Networks-on-Chip

which is devoted to:
* Architecture, modelling and design techniques for network on chip
* Design methods for the on-chip interconnection network:
interconnect topology, switching, routing and flow control methods
* Architecture and design for fault-tolerance, reliability enhancement,
quality of service, dynamic voltage and frequency scaling
* Techniques and methodologies for NoC testing
* GALS synchronization architectures for networks-on-chip
* Physical design techniques and methodologies
* Hardware/software communication abstraction, component-based modelling,
platform-based design and methodologies, NoC design space exploration frameworks
* Programming models for NoC-based platforms;
* Design of on-chip networks based on alternative technologies such as
photonics/optics, wireless, 3D stacking.

Detailed descriptions of all other topics and submission information are
found on the conference web page:
http://www.date-conference.com/authors-instructions_cfp

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TOPIC TECHNICAL COMMITTEE

Davide Bertozzi, University of Ferrara
Federico Angiolini, iNoCs
Paul Ampadu, University of Rochester
David Atienza, EPFL
Luca Benini, University of Bologna
Luca Carloni, Columbia University
Érika Cota, Universidade Federal do Rio Grande do Sul
Josè Flich, Universidad Politecnica de Valencia
Kees Goossens, Eindhoven Univ. of Technology
Ahn Jung-Ho, Seoul National University
Robert Mullins, University of Cambridge
Srinivasan Murali, IMEC India
Shaahin Hessabi, Sharif University of Technology
Sungjoo Yoo, POSTECH
Hiroki Matsutani, Keio University
Axel Jantsch, KTH
Pascal Vivet, CEA-LETI
Steven Nowick, Columbia University

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FURTHER INFORMATION

Davide Bertozzi - Track D8 Chair
University of Ferrara, Ferrara, Italy
email: dbertozzi@xxxxxxxxxxxx

Federico Angiolini - Track D8 Co-chair
iNoCs SaRL, Lausanne, Switzerland
email: angiolini@xxxxxxxxx

Lothar Thiele - DATE Program Chair
Swiss Federal Institute of Technology (ETH) Zurich, Switzerland
email: thiele@xxxxxxx